Yedidya was part of the Princeton Architecture Laboratory for Multimedia and Security (PALMS) working with Professor Ruby B. Lee. His research explored the architecture and implementation of supercomputer level bit manipulation instructions in commodity microprocessors.
In addition to being a Hertz Fellow, Yedidya held a NSF Graduate Research Fellowship and a Princeton Wu Fellowship. Yedidya is currently a Senior Design Engineer at Intel Corporation’s Massachusetts Microprocessor Design Center in Hudson, MA, where he is working on the development of next generation Xeon and Itanium server processors. His interests and research span various aspects of the design and implementation of high-performance microprocessors including performance-oriented new instructions, micro-architecture, on-chip interconnect, heterogeneous multiprocessors, logic design, cache design, timing convergence, design automation, equivalence verification, determinism and design-for-test. Yedidya is a member of the IEEE and ACM.
When not working, Yedidya enjoys biking, cooking and spending time with his wife and son.